Advanced memory technologies such as Wide I/O offer substantial improvements in performance yet have lower power consumption. A Wide I/O memory device provides four 128-bit words at a 200 MHz rate. To accommodate such a large number of input/output signals, Wide I/O memories require a very high density interconnect pitch to adjoining devices or substrates. Although organic substrates used in applications such as Package-on-Package (PoP) offer advantageously low cost, they cannot support such fine-pitch interconnections. Thus, designers are forced to interface other components to Wide I/O memories using an interposer with through substrate vias (TSVs) such as a through-silicon-via-containing silicon interposer (or alternatively, a through-glass-via-containing glass interposer). The through silicon vias are readily arranged on a silicon interposer to accommodate the fine pitch necessary for interconnections to such advanced memory devices.
FIG. 1A shows an example Wide I/O interposer system-in-package 100. As used herein, a fine-pitch die such as a Wide I/O memory is denoted as a first-pitch die 105. In contrast, a coarser-pitch die such as an SOC is referred to herein as a second-pitch die 110. To accommodate the I/O signaling between first-pitch die 105 and second-pitch die 110, both these dies are interconnected through corresponding first-pitch and second-pitch interconnects to an interposer 115. Interposer 115 includes a plurality of metal layers on a front surface facing first-pitch die 105 and second-pitch die 110. Thus, pads on first-pitch die 105 may interconnect through first-pitch interconnects such as micro-bumps to corresponding pads on interposer 115. Lateral interconnects in one or more of the metal layers on interposer 115 couple I/O signals between second-pitch die 110 and first-pitch die 105. Second-pitch die 110 may interconnect to interposer 115 through second-pitch interconnects such as thermo-compression flip-chip bumps (TCFCs). In this fashion, the majority of the I/O signaling between second-pitch die 110 and first-pitch die memory 105 may be conducted in the lateral interconnects in the metal layers on the front surface of interposer 115. The pads for these devices are not shown in FIG. 1A for illustration clarity.
Signals between second-pitch die 110 and external devices are conducted in through silicon vias 106 in interposer 115 that interconnect through second-pitch interconnects to pads on a second-pitch substrate 120 such as an organic substrate. As used herein, a “second-pitch” substrate is a substrate that can only accommodate the relatively coarser pitch for the second-pitch interconnects such as TCFCs that interconnect second-pitch die 110 to interposer 115. The external signals coupled to second-pitch substrate 120 through vias 106 as well as ground and power may then couple through vias and metal layers in second-pitch substrate 120 and bottom solder balls 107 to the external devices. A similar coupling through additional vias 106 occurs for external signals for first-pitch die 105.
Unlike second-pitch substrate 120, the interposer 115 can accommodate the fine pitch of first-pitch interconnects such as micro-bumps for interconnecting to first-pitch die 105. The majority of the signal routing between second-pitch die 110 and first-pitch die 105 thus travels through interposer 115 without any need to pass through second-pitch substrate 120. Interposer 115 interconnects to second-pitch substrate 120 through second-pitch interconnects such as copper pillar TCFCs. The cost of an interposer such as interposer 115 is dependent upon its size. The silicon or glass interposer 115 must be relatively large to receive both second-pitch die 110 and fine-pitch die 105 and is thus costly.
Because of this cost, the packaging of first-pitch dies such as Wide I/O memories with second-pitch dies such as SOCs is also accomplished using a through silicon stack (TSS) 130 as shown in FIG. 1B. In TSS 130, a second-pitch die 140 includes a plurality of through silicon vias that couple to corresponding through silicon vias in a first-pitch die 145. The through silicon vias in first-pitch die 145 in turn may couple communicate with through silicon vias in an overlying first-pitch die 150, and so on. In this fashion, a number of first-pitch dies may be stacked onto second-pitch die 140 to complete TSS 130. In general, a stacking of coupled integrated circuit devices (e.g., without wirebonding) is not limited to silicon such that other materials may be used. Thus, as used herein, the term “TSS” is not limited to just stacked silicon dies. Although TSS 130 accommodates one (or more) first-pitch memories without the need for an interposer, the TSV technology is troublesome and may have relatively poor reliability and a corresponding high defect rate.
Accordingly, there is a need in the art for improved packaging techniques to accommodate the packaging of modern first-pitch dies with second-pitch dies or other integrated circuits.